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Training, Design & Support with VHDL/Verilog

Courses	EDA Tools quick guide
o Download VHDL course presentation	o ModelSim
o Download Advanced VHDL course presentation	o Modelsim Commands Short Guide
o Computer Engineering page	o ISE & Spartan III
o Embedded Systems page	o Quartus II Quick Start
	o Debugging with Signal Tap
User Guides	o Altera DE2 user manual
o VHDL Short Command Summary (exams format)
o Verilog Coding Guidelines
o VHDL Design Methodology	Utilities
o HDL Coding Style Guide	o Generator of synthesizable CRC functions
o VHDL Handbook	o VGA Timing Calculator
o Self-Learning Page
Useful	Design examples and templates
o Emacs - the best VHDL text editor	o Download VHDL examples sources
o Download Evita (Aldec VHDL Tutorial)	o Random package
o Accellera Open Verification Library	o Generic random generator RTL
o VHDL online -> references examples and utilities	o Recursive components usage
o VHDL online Tutorial: Learn by Example	o Generic FEC with Hamming code
	o VGA template
	o Roto-Zoom Project
	o Quartus compilation Script
	o ModelSim simulation with Altera primitives
	o ModelSim Simulation Template Script (*.do file)
VHDL laboratory works	Examinations and Solutions
o Lab 1	o Exam 2009 Spring A Solution
o Lab 2	o Exam 2009 Spring B Solution
o Lab 3	o Exam 2009 Fall A Solution
o Lab 4	o Exam 2009 Fall B Solution
o Lab 5	o Exam 2010 Spring A Solution
o Lab 6	o Exam 2010 Spring B Solution
o Lab 7	o Exam 2010 Summer A Solution
o Lab 8	o Exam 2010 Summer B Solution
o Lab 9	o Exam 2010 Fall A Solution
o Labs requirements	o Exam 2010 Fall B Solution
o Lab 3 - Quartus compilation guide & script
Active HDL Tool	My Friends Sites
o Introduction to Simulation with Aldec Active HDL	o Ronen Poltek- VHDL and more

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