----------------------------------
-- DE2 Altera evaluation board
-- 50 MHz external clock, multiplied to 75 MHz by internal PLL
-- 1024x768 resolution with 70 Hz refresh rate
-- DDR FF for DAC clock output
----------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
library altera_mf ;
use altera_mf.all ;
entity vga is
generic ( current_device : string := "Cyclone II" ) ;
port
(
clk : in std_logic ; -- 50 MHz
rst : in std_logic ; -- active high
v_sync : out std_logic ; -- to monitor
h_sync : out std_logic ; -- to monitor
sync : out std_logic ; -- to DAC
blank : out std_logic ; -- to DAC
dac_clk : out std_logic ; -- to DAC
rgb : out std_logic_vector ( 29 downto 0 ) -- to monitor via DAC
) ;
attribute altera_chip_pin_lc : string ;
attribute altera_chip_pin_lc of clk : signal is "@N2" ;
attribute altera_chip_pin_lc of rst : signal is "@G26" ;
attribute altera_chip_pin_lc of dac_clk : signal is "@B8" ;
attribute altera_chip_pin_lc of blank : signal is "@D6" ;
attribute altera_chip_pin_lc of sync : signal is "@B7" ;
attribute altera_chip_pin_lc of v_sync : signal is "@D8" ;
attribute altera_chip_pin_lc of h_sync : signal is "@A7" ;
attribute altera_chip_pin_lc of rgb : signal is "@E10,@F11,@H12,@H11,@A8,@C9,@D9,@G10,@F10,@C8,@D12,@E12,@D11,@G11,@A10,@B10,@D10,@C10,@A9,@B9,@B12,@C12,@B11,@C11,@J11,@J10,@G12,@F12,@J14,@J13" ;
end entity vga ;
architecture arc_vga of vga is
-----------------------------------------------------------------------------
-- clock and reset management resources
----------------------------------------------------------------------------
signal altera_rst : std_logic ;
signal pll_clk_out : std_logic_vector ( 5 downto 0 ) ;
signal pll_clk_in : std_logic_vector ( 1 downto 0 ) ;
alias internal_clk : std_logic is pll_clk_out( 0 ) ;
signal internal_rst : std_logic ;
signal pll_locked : std_logic ;
signal dac_clk_vec : std_logic_vector ( 0 downto 0 ) ;
----------------------------------------------------------------------------
-- VGA control signals
----------------------------------------------------------------------------
signal xcnt : std_logic_vector ( 10 downto 0 ) ;
signal ycnt : std_logic_vector ( 9 downto 0 ) ;
signal dx : std_logic_vector ( 10 downto 0 ) ;
signal dy : std_logic_vector ( 9 downto 0 ) ;
----------------------------------------------------------------------------
-- VGA color constants
----------------------------------------------------------------------------
constant black : std_logic_vector ( rgb'range ) := ( others => '0' ) ;
constant blue : std_logic_vector ( rgb'range ) := ( 9 downto 0 => '1', others => '0' ) ;
constant green : std_logic_vector ( rgb'range ) := ( 19 downto 10 => '1', others => '0' ) ;
constant turquoise : std_logic_vector ( rgb'range ) := ( 19 downto 0 => '1', others => '0' ) ;
constant red : std_logic_vector ( rgb'range ) := ( 29 downto 20 => '1', others => '0' ) ;
constant purple : std_logic_vector ( rgb'range ) := ( 19 downto 10 => '0', others => '1' ) ;
constant yellow : std_logic_vector ( rgb'range ) := ( 29 downto 10 => '1', others => '0' ) ;
constant white : std_logic_vector ( rgb'range ) := ( others => '1' ) ;
----------------------------------------------------------------------------
-- Altera MF components
----------------------------------------------------------------------------
component altddio_out is
generic (
extend_oe_disable : string ;
intended_device_family : string ;
invert_output : string ;
lpm_type : string ;
oe_reg : string ;
width : natural
) ;
port (
dataout : out std_logic_vector ( 0 downto 0 ) ;
outclock : in std_logic ;
datain_h : in std_logic_vector ( 0 downto 0 ) ;
aclr : in std_logic ;
datain_l : in std_logic_vector ( 0 downto 0 )
) ;
end component altddio_out ;
component altpll is
generic (
clk0_divide_by : natural ;
clk0_duty_cycle : natural ;
clk0_multiply_by : natural ;
clk0_phase_shift : string ;
compensate_clock : string ;
gate_lock_signal : string ;
inclk0_input_frequency : natural ;
intended_device_family : string ;
invalid_lock_multiplier : natural ;
lpm_hint : string ;
lpm_type : string ;
operation_mode : string ;
port_activeclock : string ;
port_areset : string ;
port_clkbad0 : string ;
port_clkbad1 : string ;
port_clkloss : string ;
port_clkswitch : string ;
port_configupdate : string ;
port_fbin : string ;
port_inclk0 : string ;
port_inclk1 : string ;
port_locked : string ;
port_pfdena : string ;
port_phasecounterselect : string ;
port_phasedone : string ;
port_phasestep : string ;
port_phaseupdown : string ;
port_pllena : string ;
port_scanaclr : string ;
port_scanclk : string ;
port_scanclkena : string ;
port_scandata : string ;
port_scandataout : string ;
port_scandone : string ;
port_scanread : string ;
port_scanwrite : string ;
port_clk0 : string ;
port_clk1 : string ;
port_clk2 : string ;
port_clk3 : string ;
port_clk4 : string ;
port_clk5 : string ;
port_clkena0 : string ;
port_clkena1 : string ;
port_clkena2 : string ;
port_clkena3 : string ;
port_clkena4 : string ;
port_clkena5 : string ;
port_extclk0 : string ;
port_extclk1 : string ;
port_extclk2 : string ;
port_extclk3 : string ;
valid_lock_multiplier : natural
) ;
port (
inclk : in std_logic_vector ( 1 downto 0 ) ;
locked : out std_logic ;
areset : in std_logic ;
clk : out std_logic_vector ( 5 downto 0 )
) ;
end component altpll ;
begin
----------------------------------------------------------------------------
-- clock and reset management
----------------------------------------------------------------------------
dac_clk <= dac_clk_vec( 0 ) ;
altera_rst <= not internal_rst ;
internal_rst <= ( not rst ) and pll_locked ;
pll_clk_in <= '0' & ; clk;
altpll_component : altpll
generic map (
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 3,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 20000,
intended_device_family => current_device,
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
port map (
inclk => pll_clk_in,
areset => rst,
clk => pll_clk_out,
locked => pll_locked
) ;
altddio_out_component : altddio_out
generic map (
extend_oe_disable => "UNUSED",
intended_device_family => current_device,
invert_output => "OFF",
lpm_type => "altddio_out",
oe_reg => "UNUSED",
width => 1
)
port map (
outclock => internal_clk,
datain_h => "1",
aclr => altera_rst,
datain_l => "0",
dataout => dac_clk_vec
) ;
draw_picture : process( internal_clk, internal_rst ) is
begin
if ( internal_rst = '0' ) then
xcnt <= ( others => '0' ) ;
ycnt <= ( others => '0' ) ;
v_sync <= '0' ;
h_sync <= '0' ;
sync <= '0' ;
blank <= '0' ;
rgb <= black ;
elsif rising_edge ( internal_clk ) then
if ( xcnt = 1327 ) then
xcnt <= ( others => '0' ) ;
if( ycnt = 805 ) then
ycnt <= ( others => '0' ) ;
else
ycnt <= ycnt + 1 ;
end if ;
else
xcnt <= xcnt + 1 ;
end if ;
if ( xcnt > 1048 ) and ( xcnt <= 1184 )then
h_sync <= '0' ;
else
h_sync <= '1' ;
end if ;
if( ycnt > 771 ) and ( ycnt <= 777 )then
v_sync <= '0' ;
else
v_sync <= '1' ;
end if ;
if ( xcnt = 1327 ) then
xcnt <= ( others => '0' ) ;
if( ycnt = 805 ) then
ycnt <= ( others => '0' ) ;
else
ycnt <= ycnt + 1 ;
end if ;
else
xcnt <= xcnt + 1 ;
end if ;
if ( xcnt > 1048 ) and ( xcnt <= 1184 )then
h_sync <= '0' ;
else
h_sync <= '1' ;
end if ;
if( ycnt > 771 ) and ( ycnt <= 777 )then
v_sync <= '0' ;
else
v_sync <= '1' ;
end if ;
if( xcnt > 1023 ) or ( ycnt > 767 )then
sync <= '0' ;
blank <= '0' ;
rgb <= black ;
else
sync <= '0' ;
blank <= '1' ; -- should be '0' with black color
rgb <= -- any color
end if ;
end if ;
end process draw_picture ;
end architecture arc_vga ;
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